Low-Power HW Accelerator for AI Edge-Computing in Human Activity Recognition Systems
Student Contest:
Yes
Affiliation Type:
Academia
Keywords:
artificial intelligence, edge computing, hardware, low-power, human activity recognition
Abstract:
In this paper, an energy efficient HW accelerator for AI edge-computing in Human Activity Recognition is proposed. The system processes samples from a tri-axial accelerometer and classifies the human activities by using a novel Hybrid Neural Network (HNN) topology, which has been designed to reduce the computational complexity of the system while preserving its accuracy. The HW design improves the characteristics of the HNN by means of an architecture that is aimed to reduce the allocated physical resources and the memory accesses. While accuracy measured on ad-hoc dataset is 97.5 %, measurements from synthesis with CMOS 65 nm standard cells report power consumption of 6.3 μW when the sensor ouput data rate is 25 Hz, normally used for HAR.
Track ID:
10
Track Name:
AICAS in IoT, HCI, Healthcare, Autonomous Systems, Homes/Factories/Cities/Nature
