Information for Paper ID 7074
Paper Information:
Paper Title: RISC-V Processor Verification: Case Study 
Affiliation Type: Industry 
Keywords: RISC-V, verification, step-and-compare, co-debug, Specman 
Abstract: The open RISC-V instruction set architecture is gaining traction with both semiconductor vendors and systems companies. But how to verify the RISC-V processor implementation, especially when developing the RTL and/or adding custom instructions? The goal of this paper is to report on the techniques used and lessons learned for the verification of a RV64IMACBNSU RISC-V processor by an experienced SoC design team, including the development of the reference model and the SystemVerilog and C encapsulation of the reference model, the step-and-compare flow used included co-debug, and the Specman environment. 
Track ID: 1.1 
Track Name: Advanced methodologies and testbenches 
Final Decision: Accept as Lecture 
Session Name: UVM and RISC-V (Lecture) 
Author Questions:
Confirmed: Yes