Information for Paper ID 7098
Paper Information:
Paper Title: An Equivalent Modeling Approach for High-Density DRAM Array System-Level Design-Space Exploration in SystemVerilog 
Affiliation Type: Academia 
Keywords: DRAM, SystemVerilog, Retention, Array, Design Space Exploration 
Abstract: This work proposes an equivalent modeling technique for modeling a large-scale memory cell array in DRAMs in SystemVerilog and for exploring its design space considering the trade-offs between the analog characteristics with retention behavior. The key idea of this work is inspired by the fact that only one selected row of the cell array is active at any given time. Exploiting this fact, the complexity of the equivalent model and its simulation speed do not need to grow with the number of rows and efficient design space exploration is possible. 
Track ID: 5.1 
Track Name: Mixed-signal design & verification techniques 
Final Decision: Accept as Poster 
Session Name: Modeling and Patterns (Poster) 
Author Questions:
Confirmed: Yes