Information for Paper ID 7024
Paper Information:
Paper Title: Formal Verification Experiences: Spiral Refinement Methodology for Silicon Bug Hunt 
Affiliation Type: Industry 
Keywords: Formal Verification, Bug Hunt, Methodology, ASIC SOC 
Abstract: Several companies have used formal verification to perform silicon bug hunting. That is one of the most advanced usages of formal verification. It is a complex process that includes incorporating multiple sources of information and managing numerous success factors concurrently. In this paper, we will share a “spiral refinement” bug hunt methodology that captures the success factors and guides the deployment of various formal techniques. The objective is to identify the significant challenges and to gradually improve each of the factors so that we can “zero-in” on these critical bugs. 
Track ID: 1.3 
Track Name: Debug and analysis of complex designs 
Final Decision: Accept as Lecture 
Session Name: Debug and Analysis 2 (Lecture) 
Author Questions:
Confirmed: Yes