As we are investing more in automotive and safety-critical designs, there is a renewed focus on design reliability. Glitches on clock-domain-crossing (CDC) signals will undoubtedly reduce reliability and lead to potential silicon failures. Hence, CDC verification is essential at both the RTL and the gate-level. Previously, we have been focusing on preventing and catching glitches on the data multiplexing paths. After deployed gate-level CDC on several projects, we had gained more experience. We learned that it is even more critical to verify glitches on the unsynchronized and combinational CDC paths.
