Acceleration of Coreless SoC Design-Verification Using PSS on Configurable Testbench in Multi-Link PCIe Subsystems
Affiliation Type:
Industry
Keywords:
PSS, Concurrent Functional Verification, Acceleration of SoC Verification
Abstract:
Design Verification has been a highly expensive and a heavily time-consuming part of System on Chip (SoC) design flow. Design Verification challenges lie in quality of IPs, Interconnections, quality of verification vectors, runtime, timeline, tools and methodologies. We propose a solution here to accelerate the Design Verification Cycle and improve the quality of verification using PSS over Configurable SV-UVM Testbench Methodology. Using this methodology we could generate more test vectors and cover more corner cases within same duration.
Track ID:
4.3
Track Name:
Applications of the Accellera Portable Stimulus Standard
