Information for Paper ID 7081
Paper Information:
Paper Title: Lay It on Me: Creating Layered Constraints 
Affiliation Type: Industry 
Keywords: UVM, SystemVerilog, Verification 
Abstract: Today‚Äôs verification environments are complex. Creating constraints is one area of complexity for systems with complex configurations with many inter-dependent variables. As the dependencies get larger, the complexity of these inter-relationships become increasingly harder to control and understand. This paper discusses a method to solve constraints in a layered manner. This layering forces the engineer to add constraints into a specific layer and then controls the constraint solver to solve Layer N before it solves Layer N+1, repeating until all layers are solved. 
Track ID: 1.1 
Track Name: Advanced methodologies and testbenches 
Final Decision: Accept as Lecture 
Session Name: Verification Languages (Lecture) 
Author Questions:
Confirmed: Yes